The present invention relates to a semiconductor device and a control method thereof, and, for example, a semiconductor device and a control method thereof suitable for suppressing a circuit scale from being increased while maintaining a high interruption response performance.
For example, a CPU (Central Processing Unit) executes a program with a designated address among those stored in a flash memory in a microcomputer. Here, in the case where the program with the designated address is stored in a cache memory, the CPU reads the program from the cache memory, and executes the same without accessing the flash memory. On the other hand, in the case where the program with the designated address is not stored in the cache memory, the CPU transfers the program with the designated address stored in the flash memory to the cache memory, and executes the same. This is not limited to a case of a main routine program, but is also the same in the case where an interruption such as a timer interruption, a communication IP interruption, or an external terminal interruption occurs.
However, unlike the case of the main routine program, an interruption subroutine program corresponding to an interruption is not usually stored in the cache memory. Therefore, since it is necessary to access the flash memory every time an interruption occurs, there is a problem that the microcomputer cannot immediately execute the interruption subroutine program. In other words, there is a problem that the microcomputer cannot improve the responsiveness of the interruption.
A solution for such a problem is disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-24942. A microcomputer disclosed in Japanese Unexamined Patent Application Publication No. Hei 11 (1999)-24942 includes, in addition to a first command queue (cache memory) in which a main routine program is temporarily stored, a second command queue (interruption buffer memory) in which all interruption subroutine programs corresponding to a plurality of interruption factors are stored. Accordingly, since it is not necessary to access the memory (flash memory) for storing programs every time an interruption occurs, the microcomputer can improve the interruption responsiveness.